Computerized method and apparatus for designing wire bond diagrams and locating bond pads for a semiconductor device

ABSTRACT

The present invention provides a bond tool utility software package which extracts bond pad location data from a semiconductor chip design stored in one of a number of known formats (e.g., Opus, GDSII, or the like) and extracts conductor location data from an AUTOCAD file of a chip frame design. The utility retrieves bonding connection data from a design ASCII file and generates a bonding diagram for the semiconductor assembly. The utility also contains a subroutine for applying bonding design criteria to the resultant bonding diagram to determine whether all bonds are within established guidelines. If an impermissible bond is formed, the user may be alerted that one or more bonding pads may have to be relocated. In one embodiment of the present invention, the bonding utility may interface with a semiconductor design circuit to generate a suggested fix to an impermissible bonding situation. One or more bonding pads may be moved in the semiconductor design to correct for potential bonding deficiencies.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority from Provisional U.S. PatentApplication Ser. No. 60/102,970, filed Oct. 2, 1998 and incorporatedherein by reference.

FIELD OF THE INVENTION

The present invention relates to the field of computerized integratedcircuit design, in particular a computerized method and apparatus fordesigning bond diagrams and locating bond pads for a semiconductordevice.

BACKGROUND OF THE INVENTION

The design of integrated circuits is by and large a highly automatedprocess. Complex and powerful software tools are available forconverting a logic level design into a semiconductor circuit designready to be etched and formed on a semiconductor substrate.

Such programs, such as those provided by Avant! Corporation of Fremont,Calif. and Cadence Design, of San Jose, Calif. automatically routeconductors and locate components on a semiconductor chip using wellestablished rules of design as well as huge libraries of pre-storeddesign modules. Once the design for a semiconductor circuit has beencompleted, the resultant design, in a standardized electronic format(e.g., Opus, GDSII, or the like) may be transmitted to a semiconductorfabrication facility or “fab” for fabrication.

However, fabrication represents only the circuit manufacturing portionof the semiconductor manufacturing process. Once circuits are formed ona semiconductor wafer, the wafer must then be broken into a number ofdiscrete “chips” and mounted on a chip carrier with electrical leadswire-bonded from pads on the chip to conductors on the chip carrier.

Unlike the semiconductor design process, the process of designing thewire bonding layout has been largely manual. Engineers, using magnifiedcopies of chip diagrams, resort to using rulers and pencils to draw inthe locations of wire bonds. These drawn-in wire bond diagrams may thenbe used by an assembly facility to instruct a wire bonding machine as towhich pad on a chip should be connected to which lead on the chipcarrier. In some instances, not all pads may be bonded, and some leadsmay be bonded to more than one pad. Correct and accurate bondinginformation is essential to proper manufacturing of the completedcircuit.

However, such hand-drawn circuit diagrams do not lend themselves well toautomated processing. Moreover, pencilled-in diagrams may not photocopyproperly, with the result that one or more bonds may be missed orincorrectly formed. In addition, with the ever increasing number ofleads used in semiconductor devices (e.g., 128 or more), hand-drawing ofsuch bonds maybe cumbersome and error prone.

When drawing such bonds on a bonding diagram, the Engineer also usesthis opportunity to insure that the bonds comply with certainpredetermined design criteria. For example, bonds which are too long maytend to sag when encapsulated, shorting out with adjacent bonds or thechip edge. Similarly, bonds may be required to be formed only within acertain angle from the chip or at a certain distance from adjacentbonds, to prevent mechanical or electrical interference.

Manually drawing and measuring such bonds may be a tedious andinaccurate process. Using a scaled-up drawing, the Engineer must be sureto make careful measurements with a rule to insure bonds are withindesign criteria.

In addition, if one or more bonds are not within design criteria, theEngineer must move a bonding pad in the chip design in order to correctthe error. Such a move may require that the chip design be manuallyaltered through manipulation of the semiconductor circuit designprogram.

Schweiss, U.S. Pat. No. 5,155,065, issued Oct. 13, 1993, discloses amethod for configuring a plurality of pads on a semiconductor die toaccommodate more than one pad pitch. Pad sizes and pad spacings areadjusted to achieve the pad configuration, which may form a pattern.This pattern may be repeated to meet the number of pads needed in theapplication. Schweiss is cited here as background only in that itteaches various techniques for determining correct pad spacing andpitch.

Tain et al., U.S. Pat. No. 5,608,638, issued Mar. 4, 1997, discloses adevice and method for automation of a build sheet to manufacture apackaged integrated circuit. Tain et al. uses a GUI program to allow anengineer to generate buildsheet data automatically. This buildsheet dataappears to include die size, wire bonding and die image. It appears thatthe “build sheet” is directed toward a wire bonding diagram.

However, Tain et al. does not make reference to making automatedcorrections to bond pad location nor package lead layouts for qualityand yield optimization. Moreover, Tain et al., limited to a GUIapplication, makes no reference to operating system independence (i.e.,Windows™ 95/98, NT or UNIX). In addition, Tain et al., makes noreference to techniques to keep file size at a minimum, transferabilitythrough gateways, networks, or FTP sites, or towards portability of asoft file to wire bond equipment to replace manual teaching techniques.

Huddleston et. al, U.S. Pat. No. 5,498,767, issued Mar. 12, 1996,discloses a method for positioning bond pads in a semiconductor dielayout. Huddleston et al. teaches locating bond pads centers in accountwith both manufacturing and design limitations.

However, Huddleston et al. focuses only on determining wiring angle forsilicon-to-package compatibility, and does not go beyond wire anglerelated issues. Thus, for Example, Huddleston et al. does not teachdetermining die size to die attach pad compatibility, minimum andmaximum restrictions to wire length over silicon, over lead tip andoverall bond length.

Yip, et al., U.S. Pat. No. 5,465,217, issued Nov. 7, 1995, alsodiscloses an automated system for routing tape automated bonding (TAB)leads.

However, Yip et al. focusses on artwork for tape tab development basedupon a desired pad pitch. The Yip et al. technique is thus restricted totab based packages and does not encompass any semiconductor packagingand technologies for housing silicon (e.g., quad packages, dual-in-linepackages, small outline packages, and the like).

Thus, it remains a requirement in the art to provide an automatedprocess for designing bonding diagrams for semiconductor devices.

It remains a further requirement in the art to provide a technique forautomatically determining whether a bonding layout complies withestablished bonding criteria.

It remains a further requirement in the art to provide a techniquewhereby a chip design may be automatically altered if one or more bondsdo not meet established bonding criteria.

SUMMARY OF THE INVENTION

The present invention provides a bond tool utility software packagewhich extracts bond pad location data from a semiconductor chip designstored in one of a number of known formats (e.g., Opus, GDSII, or thelike) and extracts conductor location data from an AUTOCAD file of achip frame design. The utility retrieves bonding connection data from adesign ASCII file and generates a bonding diagram for the semiconductorassembly.

The utility also contains a subroutine for applying bonding designcriteria to the resultant bonding diagram to determine whether all bondsare within established guidelines. If an impermissible bond is formed,the user may be alerted that one or more bonding pads may have to berelocated.

In one embodiment of the present invention, the bonding utility mayinterface with a semiconductor design circuit to generate a suggestedfix to an impermissible bonding situation. One or more bonding pads maybe moved in the semiconductor design to correct for potential bondingdeficiencies.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a top view of an enlarged wire bonding layout diagram.

FIG. 2 is a block diagram illustrating the relationship between varioussoftware components and data elements in the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a top view of an enlarged wire bonding layout diagram. Thewire bonding diagram of FIG. 1 is an accurate scale drawing representingthe connectivity of wire bonds between a semiconductor chip 110 andpackage die 120. Package die 120 may contain groups of leads 130, 140,150, 160, which may be formed on one or more sides of the device. In theembodiment illustrated in FIG. 1, leads 130, 140, 150, and 160 areprovided on all four sides of the device. Electrical leads 130, 140,150, and 160 connect to external “pins” or contacts which connect thesemiconductor device to a wire traces on a motherboard, circuit board,SIMM or the like.

When designing a semiconductor chip, generally the package type andgeneral design constraints are known, and the package pinout selected inadvance. Thus, generally wire bonds between pad groups 135, 145, 155,and 165 on semiconductor chip 110 will not cross one another. However,it may be difficult to determine a correct location of each of the padswithin pad groups 135, 145, 155, and 165 in order to insure that wirebonds between pad groups 135, 145, 155, and 16 and corresponding leads130, 140, 150, and 160 are formed correctly.

Noted that in some instances in FIG. 1, a single pad is bonded to twoleads, or vice-versa. Note also that the pad spacing is non-uniform andmoreover is much tighter than lead spacing. Thus, each lead approachessemiconductor chip 110 at a slightly different angle. Leads located atthe corners of semiconductor chip 110 being at higher angles ofincidence than leads neat a center portion of each side of semiconductorchip 110.

If pads are incorrectly located via-a-vis their corresponding lead, awire bond may not be reliability formed or may interfere with anadjacent wire bond. For example, the angle of a wire bond withrelationship to the corder of the pad should preferably be within acertain range to insure that a proper bond is formed.

Moreover, a pad should be located within a certain distance relationshipbetween the edge of the chip over which the wire bond is formed. If thewire bond sags appreciably, it could contact the edge of the chip andcorrupt the circuitry. Standard Design Rule Checks have been establishedin industry to insure that pad and bond locations are properly located.

In the prior art, these design rule checks may have been performed byhand, and the resultant bonding diagram (similar to the one illustratedin FIG. 1) would be drawn by hand. Such a technique is time consumingand tedious and moreover prone to inaccuracies. The resultant diagrammay then be used to “teach” a wire bonding machine literally by tracingthe diagram. The machine, once programmed, would then follow such adiagram to connect wire bonds between pads and leads.

FIG. 2 is a block diagram illustrating the relationship between varioussoftware components and data elements in the present invention. Element220 represents a data file comprising a silicon bond pad layout. Siliconbond pad layout 220 may represent the location of individual pads withina semiconductor device as determined after initial circuit design. Whilesuch pads may be properly located with regard to pinout order and thelike, they may not be properly located with regard to wire bondingdesign constraints.

Silicon bond pad layout 220- may comprise a data file stored in one ormore formats used with a corresponding circuit design program. A firstformat may comprise, for example, the OPUS format 210. Opus format 210is a proprietary format of CADENCE corporation of San Jose, Calif. usedwith their proprietary circuit design software.

A second format may comprise, for example, the GDSII format 230. TheGDSII format is an industry standard format used by a number ofmanufacturers such as Avant! corporation of Fremont, Calif. and MentorGraphics, of San Jose Calif. IN addition, some proprietary softwarepackages may have conversion or output routines which allow proprietaryformat data to be output in GDSII format 230.

Depending upon the format use, a layout extraction utility amy be usedto extract pad layout design parameters from the overall circuit design.Since the detailed design of the circuitry (logic function, transistorsize and location) are of little interest in wire bonding, only the padlocation data is retrieved. OPUS layout extraction utility (OPUS SkillCode) 215 may be used to extract layout information from OPUS formatteddata 210. Layout extraction utility 235 may be used to extract data from3rd party data formats such as GDSII data 230.

Both layout extraction utilities 215 and 235 may also be fed with NetList/Pin Assignment data 240. Net List/Pin Assignment data 240 maycomprise, for example, a list in ASCII format or other database formatrepresenting the connectivity between various pins on the semiconductordevice and the corresponding bond pads. As illustrated in FIG. 1, somepins may connect to more than one bond pad and vice versa. Hence it maybe necessary to include such data in order to determine the generalbonding pattern.

From the extracted layout data and net list/pin assignment data, adatabase 250 may be created representing pay layer coordinates and pinassignments. Database 250 may include location data for each pad, aswell as the pad assignment, its connectivity to particular pins, andthose pin assignments. From such data, a wire bonding diagram may begenerated.

Package drawing 270 may comprise a CAD drawing of the resultant endpackage design (e.g., quad flat pack or the like). Package drawing 270data may be fed to autocad program 265 which may be modified by aC-program utility to generate package information 285. Packageinformation 285 may comprise that portion of package drawing 270 whichillustrates the location of leads 130, 140, 150, and 160.

Package information 285 and database 250 may then be fed to C-programutility 260. C-program utility 260 receives pad layer coordinates andpin assignment from database 250 and package information data 285 andfeed all data through design rule check utility 255. Design rule checkutility 255 may comprise a C-program which will check angles anddistances of leads from the package leads to silicon pads and determinewhether a rule violation has occurred.

If a bonding rule violation has occurred, C-program utility 260 may doone of two things. First, a user may be alerted of the violation andallowed the opportunity to correct the violation manually. The user maythen utilize AUTOCAD drafting software to move a silicon pad to correctthe design rule violation. The revised AUTOCAD file may then be fed backthrough C-program utility and design rule check utility to determinewhether the revised design contains and bonding rule errors.

In a second technique, C-program utility may be programmed toautomatically correct for bonding rule errors by relocating pads on thesilicon design. In either instance, once the bonding diagram meets alldesign rule criteria, an AUTOCAD file 275 may be produced comprising therevised bonding diagram. AUTOCAD file 275 may be fed to AUTOCAD utility280, which may comprise custom code, to output a bonding diagram 285.

AutoCad utility 280 may also output corrected pad location data tocircuit design program interface 290. Circuit design program interface290 may comprise a C-program utility patch to one of a number of circuitdesign programs offered by a number of providers (e.g., Cadence, Avant!,or the like). Circuit design program interface 290 may alter the datafile for the circuit design to correct the silicon bond pay layout inview of any design rule violations previously detected.

While the preferred embodiment and various alternative embodiments ofthe invention have been disclosed and described in detail herein, it maybe apparent to those skilled in the art that various changes in form anddetail may be made therein without departing from the spirit and scopethereof.

What is claimed is:
 1. A computerized automatic method for generating awire bonding diagram for a semiconductor device, said method comprisingthe steps of: generating, in a computer, pad layer coordinates and pinassignments from semiconductor design data; generating, in a computer,package information from semiconductor package drawing information;generating, in a computer, wire bonding diagram data from the extractedpackage information and the pad layer coordinates and pin assignments;automatically checking, with a computer program, the wire bondingdiagram data against a design rule database comprising a predeterminedset of wire bonding rules to determine whether any wire bonds violateone or more of the predetermined set wire bonding rules; automaticallyadjusting location of one or more pads in the semiconductor design inresponse to any violation of the predetermined set of wire bondingrules; and automatically generating a bonding diagram databaserepresenting locations of wire bonds for the semiconductor device. 2.The method of claim 1, wherein said step of generating pad layercoordinates and pin assignments from semiconductor design data comprisesthe steps of: receiving, from a circuit design computer program, acircuit design database representing a circuit design of thesemiconductor device; receiving a pin assignment database representingpin assignments for the semiconductor device; and extracting, using acomputer program, pad layer coordinates and pin assignments from thefrom the circuit design database and the pin assignment database.
 3. Themethod of claim 2, wherein said step of generating package informationfrom semiconductor package drawing information comprises the steps of:receiving a drawing database comprising a drawing of a package designfor the semiconductor device; and extracting, using a computer program,package information from the drawing database.
 4. The method of claim 2,further comprising the steps of: outputting adjusted locations of one ormore pads in the circuit design adjusted in response to any violation ofthe predetermined set of wire bonding rules to an interface program;converting the adjusted locations of the one or more pads into a dataformat compatible with the circuit design computer program; and revisingthe first database to reflect the adjusted locations of the one or morepads.
 5. A series of steps to be performed by a computer for generatinga bonding diagram for a semiconductor device, comprising the steps of:generating, from semiconductor design data, a first data file comprisingpad layer coordinates of the semiconductor device and pin assignmentsfor a semiconductor package; generating, from semiconductor packagedrawing data, a second data file comprising package lead location data;generating, from the first and second data files, a third data filecomprising wire bonding diagram data; checking the wire bonding diagramdata against a design rule database comprising a predetermined set ofwire bonding rules to determine whether any wire bonds violate one ormore of the predetermined set wire bonding rules; adjusting location ofone or more pads in the wire bonding diagram data in the third data filein response to any violation of the predetermined set of wire bondingrules; and outputting the wire bonding diagram data in the third datafile representing locations of wire bonds for the semiconductor device.6. The series of steps to be performed by a computer for generating abonding diagram for a semiconductor device of claim 5, wherein said stepof generating the first data file comprises the steps of: receiving,from a circuit design computer program, a circuit design databaserepresenting a circuit design of the semiconductor device; receiving apin assignment database representing pin assignments for thesemiconductor device; and extracting pad layer coordinates and pinassignments from the from the circuit design database and the pinassignment database.
 7. The series of steps to be performed by acomputer for generating a bonding diagram for a semiconductor device ofclaim 6, wherein said step of generating the second data file comprisesthe steps of: receiving a drawing database comprising a drawing of apackage design for the semiconductor device; and extracting packageinformation from the drawing database.
 8. The series of steps to beperformed by a computer for generating a bonding diagram for asemiconductor device of claim 6, further comprising the steps of:outputting adjusted locations of one or more pads in the circuit designadjusted in response to any violation of the predetermined set of wirebonding rules to an interface program; converting the adjusted locationsof the one or more pads into a data format compatible with the circuitdesign computer program; and revising the first database to reflect theadjusted locations of the one or more pads.
 9. An apparatus forgenerating a wire bonding diagram for a semiconductor device,comprising: first means for generating pad layer coordinates and pinassignments from semiconductor design data; second means for generatingpackage information from semiconductor package drawing information;third means, coupled to said first and second means, for generating wirebonding diagram data from the extracted package information and the padlayer coordinates and pin assignments; fourth means for checking thewire bonding diagram data against a design rule database comprising apredetermined set of wire bonding rules to determine whether any wirebonds violate one or more of the predetermined set wire bonding rules;fifth means for adjusting location of one or more pads in thesemiconductor design in response to any violation of the predeterminedset of wire bonding rules; and sixth means for generating a bondingdiagram database representing locations of wire bonds for thesemiconductor device.
 10. The apparatus of claim 9, wherein said firstmeans for generating pad layer coordinates and pin assignments fromsemiconductor design data comprises: means for receiving, from a circuitdesign computer program, a circuit design database representing acircuit design of the semiconductor device; means for receiving a pinassignment database representing pin assignments for the semiconductordevice; and a computer program for extracting pad layer coordinates andpin assignments from the from the circuit design database and the pinassignment database.
 11. The apparatus of claim 9, wherein said secondmeans for generating package information from semiconductor packagedrawing information comprises: means for receiving a drawing databasecomprising a drawing of a package design for the semiconductor device;and a computer program for extracting package information from thedrawing database.
 12. The apparatus of claim 9, further comprising:means for outputting adjusted locations of one or more pads in thecircuit design adjusted in response to any violation of thepredetermined set of wire bonding rules to an interface program; meansfor converting the adjusted locations of the one or more pads into adata format compatible with the circuit design computer program; andmeans for revising the first database to reflect the adjusted locationsof the one or more pads.
 13. A computer program for use withsemiconductor circuit design program data and computer generated designdrafting data of a semiconductor package, the computer programcomprising: a first portion, receiving the semiconductor circuit designprogram data and a net list pin assignment data file, for extracting padlayer coordinates and pin assignments; a second portion, receiving thedesign drafting data of a semiconductor package, for generating packagelead location information; a third portion, receiving the extracted paylayer coordinates and pin assignments and package lead locationinformation and generating wire bonding diagram data; a fourth portion,receiving the wire bonding diagram data and checking the wire bondingdiagram data against a design rule database comprising a predeterminedset of wire bonding rules to determine whether any wire bonds violateone or more of the predetermined set wire bonding rules; and a fifthportion, for adjusting location of one or more pads layer coordinates inresponse to any violation of the predetermined set of wire bondingrules.
 14. The computer program of claim 13, wherein said first portioncomprises: means for receiving, from a semiconductor circuit designcomputer program, the semiconductor circuit design program datarepresenting a circuit design of the semiconductor device; means forreceiving a pin assignment database representing pin assignments for thesemiconductor device; and means for extracting pad layer coordinates andpin assignments from the from the semiconductor circuit design programdata and the pin assignment database.
 15. The computer program of claim14, wherein said second portion comprises: means for receiving a drawingdatabase comprising a drawing of a package design for the semiconductordevice; and means for extracting package lead location information fromthe drawing database.
 16. The computer program of claim 13, furthercomprising: a sixth portion for outputting adjusted locations of one ormore pad layer coordinates in the circuit design adjusted in response toany violation of the predetermined set of wire bonding rules to aninterface program; a seventh portion for converting the adjustedlocations of the one or more pad layer coordinates into a data formatcompatible with the semiconductor circuit design computer program data;and means for revising the semiconductor circuit design program datareflect adjusted locations of the one or more pad layer coordinates.